Metal oxide semiconductor (MOS) devices are well known. Field effect transistors (FET) MOS devices are also well known and are generally referred to as MOSFETs. For example, a n-channel MOSFET consists of a lightly doped p-well formed on a n-type substrate. Two highly doped n.sup.+ regions are diffused. One of the n.sup.+ regions is connected to a conductor and is referred to as a source (S). The other of the n.sup.+ regions is connected to another conductor and is referred to as a drain (D). Between the source and the drain, another conductor is positioned which is known as the gate (G). The source and the drain are diffused into the silicon and the gate sits atop an insulating layer, generally a silicon dioxide layer. In essence, the gate is charged so as to induce a n-channel between the two separated n.sup.+ regions of the MOSFET. This will produce an enhancement type MOS device. P-channel MOSFETs can similarly be constructed.
Charge pumps are circuit elements using the pumping action of diode connected MOSFETs and MOS capacitors to provide a voltage source of higher voltage than the power supplies. A diode connected MOSFET (known also as a MOSFET diode or a MOS transistor diode) is a MOS transistor with its gate and drain terminals shorted to each other. By applying an oscillating voltage to the tied source and drain terminals of the MOS capacitor, a successively higher voltage is induced at the source terminal of the MOS transistor diode with time, until a steady state voltage is reached.
The charge pumping effect may be achieved by a MOS capacitor, which is a MOSFET with its source and drain terminals shorted to each other, and with its gate terminal connected to a MOS transistor diode and its p-wells connected to ground voltage. In this case, the gate conductor forms one plate of the capacitor. As it is well known, MOS devices have three basic states of operation: inversion, depletion and accumulation. In case of a n-channel MOS device, inversion occurs when the voltage VGS between G and S is greater than a certain threshold voltage, V.sub.T which is characterized by the design and fabrication process of the device. When inversion occurs, a n-channel connecting the source and drain region is induced at the top of the p-well underneath the gate. The effective capacitance of the MOS capacitor is that of the source-drain to gate capacitance in parallel with the n-channel to gate capacitance, which is equal to the sum of the two capacitors. Depletion or accumulation occurs when V.sub.GS is less than V.sub.T. When depletion or accumulation occurs, no channel is induced. The effective capacitance of the MOS capacitor is that of the source-drain to gate capacitance alone, which is significantly less than the effective capacitance when the MOS capacitor is in the inversion state. Typically, prior charge pumps are used to provide a voltage source substantially higher than the power supply voltage (VDD) which is normally at 5.0 volts, with a tolerance of +/-0.5 volts. With a 5.0 volts power supply voltage, the MOS capacitor can be driven into inversion state easily and accordingly, sufficient effective capacitance is provided for charge pumping action.
Presently, however, electronic technology is heading toward reducing the power consumption of integrated circuit chip, and thus a reduced VDD, which is typically 3.3 volts with a tolerance +/-0.3 volts, is becoming more popular. In such a situation, the prior art charge pump mechanism is limited. When the power supply voltage is at 3.3 volts, the effective capacitance obtainable with an MOS capacitor is drastically reduced as previously explained because V.sub.GS is now closer to the V.sub.T of the MOS transistor. Instead of maintaining the MOS capacitor at inversion state, the MOS capacitor may remain at either depletion or accumulation state which results in a significant reduction of its effective capacitance. As the capacitance goes down, the output voltage will be reduced accordingly. Thus the prior art charge pump is not able to provide the output voltage at the desired level. There have been attempts made in the prior art to relieve the problem by replacing MOS capacitor with a double polysilicon capacitor structure, where each polysilicon structure forms the respective plate of the capacitor. While a double polysilicon capacitor can provide the desired capacitance when the supply voltage is at a lower voltage, the additional steps associated with forming double polysilicon capacitor structures complicate the wafer fabrication process and increase the cost of manufacturing.
Accordingly, it would be desirable to provide an improved charge pump which can operate under low voltage power supply condition without increasing its complexity. It is also desirable to provide an improved charge pump which can operate without signifcantly increasing the cost of the manufacturing process. The present invention addresses such a need.